F16C

The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats.

History

The CVT16 instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set.

CVT16 is a revision of part of the SSE5 instruction set proposal announced on August 30, 2007, which is supplemented by the XOP and FMA4 instruction sets. This revision makes the binary coding of the proposed new instructions more compatible with Intel's AVX instruction extensions, while the functionality of the instructions is unchanged.

In recent documents, the name F16C is formally used in both Intel and AMD x86-64 architecture specifications.

Technical information

There are variants that convert four floating-point values in an XMM register or 8 floating-point values in a YMM register.

The instructions are abbreviations for "vector convert packed half to packed single" and vice versa:

VCVTPH2PS xmmreg,xmmrm64 – convert four half-precision floating point values in memory or the bottom half of an XMM register to four single-precision floating-point values in an XMM register.
VCVTPH2PS ymmreg,xmmrm128 – convert eight half-precision floating point values in memory or an XMM register (the bottom half of a YMM register) to eight single-precision floating-point values in a YMM register.
VCVTPS2PH xmmrm64,xmmreg,imm8 – convert four single-precision floating point values in an XMM register to half-precision floating-point values in memory or the bottom half an XMM register.
VCVTPS2PH xmmrm128,ymmreg,imm8 – convert eight single-precision floating point values in a YMM register to half-precision floating-point values in memory or an XMM register.

The 8-bit immediate argument to VCVTPS2PH selects the rounding mode. Values 0–4 select nearest, down, up, truncate, and the mode set in MXCSR.RC.

Support for these instructions is indicated by bit 29 of ECX after CPUID with EAX=1.

AMD technology

Platforms	Spider Dragon Horus

Technology	Cool'n'Quiet High Bandwidth Memory PowerNow! PowerPlay PowerTune Turbo Core ASTC

Instructions	3DNow! AVX XOP CVT16/F16C FMA FMA3 FMA4 BMI ABM BMI1 TBM SSE5 ASF AES

Intel technology

Platforms	Centrino Centrino 2 vPro Viiv MID Tablet CULV Ultrabook Skulltrail NUC Galileo Edison Curie

Discontinued	Common Building Block MultiProcessor Specification Intel Communication Streaming Architecture Intel Inboard 386 Intel Play MMC-1 MMC-2

Current	Advanced Programmable Interrupt Controller APIC x2APIC Active Management Technology AMT versions High-bandwidth Digital Content Protection High Definition Audio Hub Architecture Matrix RAID I/O Controller Hub SpeedStep Serial Digital Video Out Host Embedded Controller Interface Platform Environment Control Interface QuickPath Interconnect Platform Controller Hub System Management Bus Thunderbolt

Upcoming	Silicon Photonics Link

Instruction set extensions

SIMD (RISC)	DEC Alpha MVI ARM NEON MIPS MDMX MIPS-3D MXU PA-RISC MAX Power Architecture AltiVec SPARC VIS

SIMD (x86)	MMX (1996) 3DNow! (1998) SSE (1999) SSE2 (2001) SSE3 (2004) SSSE3 (2006) SSE4 (2006) SSE5 ~~(2007)~~ AVX (2008) F16C (2009) XOP (2009) CLMUL (2010) FMA (FMA4: 2011, FMA3: 2012) AVX-512 (2015)

Bit manipulation	BMI (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)

Security and Cryptography	AES-NI (2008); 32- and 64-bit ARMv8 also has AES instructions SHA (2013) MPX (2015) SGX (2015)

Transactional memory	TSX (2013) ASF

Virtualization	VT-x (2005) AMD-V (2006)

Suspended extensions' dates have been ~~struck through~~.

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F16C

History

Technical information

External links