Finite-state machine

"State machine" redirects here. For infinite state machines, see State transition system. For fault-tolerance methodology, see State machine replication.

"SFSM" redirects here. For the Italian railway company, see Circumvesuviana.

"Finite Automata" redirects here. For the electro-industrial group, see Finite Automata (band).

Classes of automata

A finite-state machine (FSM) or finite-state automaton (FSA, plural: automata), or simply a state machine, is a mathematical model of computation used to design both computer programs and sequential logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time; the state it is in at any given time is called the current state. It can change from one state to another when initiated by a triggering event or condition; this is called a transition. A particular FSM is defined by a list of its states, its initial state, and the triggering condition for each transition.

The behavior of state machines can be observed in many devices in modern society that perform a predetermined sequence of actions depending on a sequence of events with which they are presented. Simple examples are vending machines, which dispense products when the proper combination of coins is deposited, elevators, whose sequence of stops is determined by the floors requested by riders, traffic lights, which change sequence when cars are waiting, and combination locks, which require the input of combination numbers in the proper order.

Finite-state machines can model a large number of problems, among which are electronic design automation, communication protocol design, language parsing and other engineering applications. In biology and artificial intelligence research, state machines or hierarchies of state machines have been used to describe neurological systems. In linguistics, they are used to describe simple parts of the grammars of natural languages.

Considered as an abstract model of computation, the finite state machine has less computational power than some other models of computation such as the Turing machine.^[1] That is, there are tasks that no FSM can do, but some Turing machines can. This is because an FSM's memory is limited by the number of states it has.

FSMs are studied in the more general field of automata theory.

Example: coin-operated turnstile

State diagram for a turnstile

A turnstile

An example of a very simple mechanism that can be modeled by a state machine is a turnstile.^[2]^[3] A turnstile, used to control access to subways and amusement park rides, is a gate with three rotating arms at waist height, one across the entryway. Initially the arms are locked, blocking the entry, preventing patrons from passing through. Depositing a coin or token in a slot on the turnstile unlocks the arms, allowing a single customer to push through. After the customer passes through, the arms are locked again until another coin is inserted.

Considered as a state machine, the turnstile has two states: Locked and Unlocked.^[2] There are two inputs that affect its state: putting a coin in the slot (coin) and pushing the arm (push). In the locked state, pushing on the arm has no effect; no matter how many times the input push is given, it stays in the locked state. Putting a coin in – that is, giving the machine a coin input – shifts the state from Locked to Unlocked. In the unlocked state, putting additional coins in has no effect; that is, giving additional coin inputs does not change the state. However, a customer pushing through the arms, giving a push input, shifts the state back to Locked.

The turnstile state machine can be represented by a state transition table, showing for each state the new state and the output (action) resulting from each input

Current State	Input	Next State	Output
Locked	coin	Unlocked	Unlock turnstile so customer can push through
Locked	push	Locked	None
Unlocked	coin	Unlocked	None
Unlocked	push	Locked	When customer has pushed through, lock turnstile

It can also be represented by a directed graph called a state diagram (above). Each of the states is represented by a node (circle). Edges (arrows) show the transitions from one state to another. Each arrow is labeled with the input that triggers that transition. Inputs that don't cause a change of state (such as a coin input in the Unlocked state) are represented by a circular arrow returning to the original state. The arrow into the Locked node from the black dot indicates it is the initial state.

Concepts and terminology

A state is a description of the status of a system that is waiting to execute a transition. A transition is a set of actions to be executed when a condition is fulfilled or when an event is received. For example, when using an audio system to listen to the radio (the system is in the "radio" state), receiving a "next" stimulus results in moving to the next station. When the system is in the "CD" state, the "next" stimulus results in moving to the next track. Identical stimuli trigger different actions depending on the current state.

In some finite-state machine representations, it is also possible to associate actions with a state:

Entry action: performed when entering the state,
Exit action: performed when exiting the state.

Representations

Fig. 1 UML state chart example (a toaster oven)

Fig. 2 SDL state machine example

Fig. 3 Example of a simple finite state machine

For an introduction, see State diagram.

State/Event table

Several state transition table types are used. The most common representation is shown below: the combination of current state (e.g. B) and input (e.g. Y) shows the next state (e.g. C). The complete action's information is not directly described in the table and can only be added using footnotes. A FSM definition including the full actions information is possible using state tables (see also virtual finite-state machine).

State transition table
Current state Input	State A	State B	State C
Input X	…	…	…
Input Y	…	State C	…
Input Z	…	…	…

UML state machines

The Unified Modeling Language has a notation for describing state machines. UML state machines overcome the limitations of traditional finite state machines while retaining their main benefits. UML state machines introduce the new concepts of hierarchically nested states and orthogonal regions, while extending the notion of actions. UML state machines have the characteristics of both Mealy machines and Moore machines. They support actions that depend on both the state of the system and the triggering event, as in Mealy machines, as well as entry and exit actions, which are associated with states rather than transitions, as in Moore machines.

SDL state machines

The Specification and Description Language is a standard from ITU that includes graphical symbols to describe actions in the transition:

send an event
receive an event
start a timer
cancel a timer
start another concurrent state machine
decision

SDL embeds basic data types called Abstract Data Types, an action language, and an execution semantic in order to make the finite state machine executable.

Other state diagrams

There are a large number of variants to represent an FSM such as the one in figure 3.

Usage

In addition to their use in modeling reactive systems presented here, finite state automata are significant in many different areas, including electrical engineering, linguistics, computer science, philosophy, biology, mathematics, and logic. Finite state machines are a class of automata studied in automata theory and the theory of computation. In computer science, finite state machines are widely used in modeling of application behavior, design of hardware digital systems, software engineering, compilers, network protocols, and the study of computation and languages.

Classification

The state machines can be subdivided into transducers, acceptors, classifiers and sequencers.^[4]

Acceptors and recognizers

Fig. 4 Acceptor FSM: parsing the string "nice"

Acceptors (also called recognizers and sequence detectors) produce binary output, indicating whether or not received input is accepted. Each state of an FSM is either "accepting" or "not accepting". Once all input has been received, if the current state is an accepting state, the input is accepted; otherwise it is rejected. As a rule, input is a series of symbols (characters); actions are not used. The example in figure 4 shows a finite state machine that accepts the string "nice". In this FSM, the only accepting state is state 7.

A machine could also be described as defining a language, that would contain every string accepted by the machine but none of the rejected ones; that language is "accepted" by the machine. By definition, the languages accepted by FSMs are the regular languages—; a language is regular if there is some FSM that accepts it.

The problem of determining the language accepted by a given FSA is an instance of the algebraic path problem—itself a generalization of the shortest path problem to graphs with edges weighted by the elements of an (arbitrary) semiring.^[5]^[6]^[7]

Start state

The start state is usually shown drawn with an arrow "pointing at it from any where" (Sipser (2006) p. 34).

Accept (or final) states

Fig. 5: Representation of a finite-state machine; this example shows one that determines whether a binary number has an even number of 0s, where

S_{1}

is an accepting state.

Accept states (also referred to as accepting or final states) are those at which the machine reports that the input string, as processed so far, is a member of the language it accepts. Accepting states are usually represented by double circles.

The start state can also be an accepting state, in which case the automaton accepts the empty string. If the start state is not an accepting state and there are no connecting edges to any of the accepting states, then the automaton is accepting nothing.

An example of an accepting state appears in Fig.5: a deterministic finite automaton (DFA) that detects whether the binary input string contains an even number of 0s.

S₁ (which is also the start state) indicates the state at which an even number of 0s has been input. S₁ is therefore an accepting state. This machine will finish in an accept state, if the binary string contains an even number of 0s (including any binary string containing no 0s). Examples of strings accepted by this DFA are ε (the empty string), 1, 11, 11…, 00, 010, 1010, 10110, etc…

Classifier is a generalization that, similar to acceptor, produces single output when terminates but has more than two terminal states.

Transducers

Fig. 6 Transducer FSM: Moore model example

Main article: Finite-state transducer

Transducers generate output based on a given input and/or a state using actions. They are used for control applications and in the field of computational linguistics.

In control applications, two types are distinguished:

Moore machine: The FSM uses only entry actions, i.e., output depends only on the state. The advantage of the Moore model is a simplification of the behaviour. Consider an elevator door. The state machine recognizes two commands: "command_open" and "command_close", which trigger state changes. The entry action (E:) in state "Opening" starts a motor opening the door, the entry action in state "Closing" starts a motor in the other direction closing the door. States "Opened" and "Closed" stop the motor when fully opened or closed. They signal to the outside world (e.g., to other state machines) the situation: "door is open" or "door is closed".

Fig. 7 Transducer FSM: Mealy model example

Mealy machine: The FSM uses only input actions, i.e., output depends on input and state. The use of a Mealy FSM leads often to a reduction of the number of states. The example in figure 7 shows a Mealy FSM implementing the same behaviour as in the Moore example (the behaviour depends on the implemented FSM execution model and will work, e.g., for virtual FSM but not for event-driven FSM). There are two input actions (I:): "start motor to close the door if command_close arrives" and "start motor in the other direction to open the door if command_open arrives". The "opening" and "closing" intermediate states are not shown.

Generators

The sequencers or generators are a subclass of aforementioned types that have a single-letter input alphabet. They produce only one sequence, which can be interpreted as output sequence of transducer or classifier outputs.

Determinism

A further distinction is between deterministic (DFA) and non-deterministic (NFA, GNFA) automata. In deterministic automata, every state has exactly one transition for each possible input. In non-deterministic automata, an input can lead to one, more than one or no transition for a given state. This distinction is relevant in practice, but not in theory, as there exists an algorithm (the powerset construction) that can transform any NFA into a more complex DFA with identical functionality.

The FSM with only one state is called a combinatorial FSM and uses only input actions. This concept is useful in cases where a number of FSM are required to work together, and where it is convenient to consider a purely combinatorial part as a form of FSM to suit the design tools.^[8]

Alternative semantics

There are other sets of semantics available to represent state machines. For example, there are tools for modeling and designing logic for embedded controllers.^[9] They combine hierarchical state machines, flow graphs, and truth tables into one language, resulting in a different formalism and set of semantics.^[10] Figure 8 illustrates this mix of state machines and flow graphs with a set of states to represent the state of a stopwatch and a flow graph to control the ticks of the watch. These charts, like Harel's original state machines,^[11] support hierarchically nested states, orthogonal regions, state actions, and transition actions.^[12]

FSM logic

Fig. 8 FSM Logic (Mealy)

The next state and output of an FSM is a function of the input and of the current state. The FSM logic is shown in Figure 8.

Mathematical model

In accordance with the general classification, the following formal definitions are found:

A deterministic finite state machine or acceptor deterministic finite state machine is a quintuple $(\Sigma ,S,s_{0},\delta ,F)$ , where:
- $\Sigma$ is the input alphabet (a finite, non-empty set of symbols).
- $S$ is a finite, non-empty set of states.
- $s_{0}$ is an initial state, an element of $S$ .
- $\delta$ is the state-transition function: $\delta :S\times \Sigma \rightarrow S$ (in a nondeterministic finite automaton it would be $\delta :S\times \Sigma \rightarrow {\mathcal {P}}(S)$ , i.e., $\delta$ would return a set of states).
- $F$ is the set of final states, a (possibly empty) subset of $S$ .

For both deterministic and non-deterministic FSMs, it is conventional to allow $\delta$ to be a partial function, i.e. $\delta (q,x)$ does not have to be defined for every combination of $q\in S$ and $x\in \Sigma$ . If an FSM $M$ is in a state $q$ , the next symbol is $x$ and $\delta (q,x)$ is not defined, then $M$ can announce an error (i.e. reject the input). This is useful in definitions of general state machines, but less useful when transforming the machine. Some algorithms in their default form may require total functions.

A finite-state machine is a restricted Turing machine where the head can only perform "read" operations, and always moves from left to right.^[13]

A finite state transducer is a sextuple $(\Sigma ,\Gamma ,S,s_{0},\delta ,\omega )$ , where:
- $\Sigma$ is the input alphabet (a finite non-empty set of symbols).
- $\Gamma$ is the output alphabet (a finite, non-empty set of symbols).
- $S$ is a finite, non-empty set of states.
- $s_{0}$ is the initial state, an element of $S$ . In a nondeterministic finite automaton, $s_{0}$ is a set of initial states.
- $\delta$ is the state-transition function: $\delta :S\times \Sigma \rightarrow S$ .
- $\omega$ is the output function.

If the output function is a function of a state and input alphabet ( $\omega :S\times \Sigma \rightarrow \Gamma$ ) that definition corresponds to the Mealy model, and can be modelled as a Mealy machine. If the output function depends only on a state ( $\omega :S\rightarrow \Gamma$ ) that definition corresponds to the Moore model, and can be modelled as a Moore machine. A finite-state machine with no output function at all is known as a semiautomaton or transition system.

If we disregard the first output symbol of a Moore machine, $\omega (s_{0})$ , then it can be readily converted to an output-equivalent Mealy machine by setting the output function of every Mealy transition (i.e. labeling every edge) with the output symbol given of the destination Moore state. The converse transformation is less straightforward because a Mealy machine state may have different output labels on its incoming transitions (edges). Every such state needs to be split in multiple Moore machine states, one for every incident output symbol.^[14]

Optimization

Main article: DFA minimization

Optimizing an FSM means finding the machine with the minimum number of states that performs the same function. The fastest known algorithm doing this is the Hopcroft minimization algorithm.^[15]^[16] Other techniques include using an implication table, or the Moore reduction procedure. Additionally, acyclic FSAs can be minimized in linear time.^[17]

Implementation

Hardware applications

Fig. 9 The circuit diagram for a 4-bit TTL counter, a type of state machine

In a digital circuit, an FSM may be built using a programmable logic device, a programmable logic controller, logic gates and flip flops or relays. More specifically, a hardware implementation requires a register to store state variables, a block of combinational logic that determines the state transition, and a second block of combinational logic that determines the output of an FSM. One of the classic hardware implementations is the Richards controller.

A particular case of Moore FSM, when output is directly connected to the state flip-flops, that is when output function is simple identity, is known as Medvedev FSM.^[18] It is advised in chip design that no logic is placed between primary I/O and registers to minimize interchip delays, which are usually long and limit the FSM frequencies.

Through state encoding for low power state machines may be optimized to minimize power consumption.

Software applications

The following concepts are commonly used to build software applications with finite state machines:

Finite automata and compilers

Finite automata are often used in the frontend of programming language compilers. Such a frontend may comprise several finite state machines that implement a lexical analyzer and a parser. Starting from a sequence of characters, the lexical analyzer builds a sequence of language tokens (such as reserved words, literals, and identifiers) from which the parser builds a syntax tree. The lexical analyzer and the parser handle the regular and context-free parts of the programming language's grammar.^[19]

References

↑ Belzer, Jack; Holzman, Albert George; Kent, Allen (1975). Encyclopedia of Computer Science and Technology, Vol. 25. USA: CRC Press. p. 73. ISBN 0-8247-2275-2.
1 2 Koshy, Thomas (2004). Discrete Mathematics With Applications. Academic Press. p. 762. ISBN 0-12-421180-1.
↑ Wright, David R. (2005). "Finite State Machines" (PDF). CSC215 Class Notes. Prof. David R. Wright website, N. Carolina State Univ. Retrieved July 14, 2012.
↑ Keller, Robert M. (2001). "Classifiers, Acceptors, Transducers, and Sequencers" (PDF). Computer Science: Abstraction to Implementation (PDF). Harvey Mudd College. p. 480.
↑ Pouly, Marc; Kohlas, Jürg (2011). Generic Inference: A Unifying Theory for Automated Reasoning. John Wiley & Sons. Chapter 6. Valuation Algebras for Path Problems, p. 223 in particular. ISBN 978-1-118-01086-0.
↑ Storer, J. A. (2001). An Introduction to Data Structures and Algorithms. Springer Science & Business Media. p. 337. ISBN 978-0-8176-4253-2.
↑ http://www.iam.unibe.ch/~run/talks/2008-06-05-Bern-Jonczy.pdf, p. 34
↑ Brutscheck, M., Berger, S., Franke, M., Schwarzbacher, A., Becker, S.: Structural Division Procedure for Efficient IC Analysis. IET Irish Signals and Systems Conference, (ISSC 2008), pp.18-23. Galway, Ireland, 18–19 June 2008.
↑ Tiwari, A. (2002). Formal Semantics and Analysis Methods for Simulink Stateflow Models.
↑ Hamon, G. (2005). A Denotational Semantics for Stateflow. International Conference on Embedded Software. Jersey City, NJ: ACM. pp. 164–172. CiteSeerX 10.1.1.89.8817.
↑ Harel, D. (1987). A Visual Formalism for Complex Systems. Science of Computer Programming , 231–274.
↑ Alur, R., Kanade, A., Ramesh, S., & Shashidhar, K. C. (2008). Symbolic analysis for improving simulation coverage of Simulink/Stateflow models. International Conference on Embedded Software (pp. 89–98). Atlanta, GA: ACM.
↑ Black, Paul E (12 May 2008). "Finite State Machine". Dictionary of Algorithms and Data Structures. U.S. National Institute of Standards and Technology.
↑ Anderson, James Andrew; Head, Thomas J. (2006). Automata theory with modern applications. Cambridge University Press. pp. 105–108. ISBN 978-0-521-84887-9.
↑ Hopcroft, John E. (1971). An n log n algorithm for minimizing states in a finite automaton (PDF) (Technical Report). CS-TR-71-190. Stanford Univ.
↑ Almeida, Marco; Moreira, Nelma; Reis, Rogerio (2007). On the performance of automata minimization algorithms (PDF) (Technical Report). DCC-2007-03. Porto Univ.
↑ Revuz, D. (1992). "Minimization of Acyclic automata in Linear Time". Theoretical Computer Science. Elsevier. 92: 181–189. doi:10.1016/0304-3975(92)90142-3.
↑ Kaeslin, Hubert (2008). "Mealy, Moore, Medvedev-type and combinatorial output bits". Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication. Cambridge University Press. p. 787. ISBN 978-0-521-88267-5.
↑ Aho, Alfred V.; Sethi, Ravi; Ullman, Jeffrey D. (1986). Compilers: Principles, Techniques, and Tools (1st ed.). Addison-Wesley. ISBN 978-0-201-10088-4.

External links

Wikimedia Commons has media related to Finite state machine.

Finite State Automata at DMOZ
Modeling a Simple AI behavior using a Finite State Machine Example of usage in Video Games
Free On-Line Dictionary of Computing description of Finite State Machines
NIST Dictionary of Algorithms and Data Structures description of Finite State Machines
Interactive FSM: Control Circuit, demonstrates the logic flow of the Finite State Machines.
FSM simulator, simulates DFAs, NFAs and ε-NFAs, including generated by regular expression.

Automata theory: formal languages and formal grammars

Chomsky hierarchy	Grammars	Languages	Abstract machines

Type-0 — Type-1 — — — — — Type-2 — — Type-3 — —	Unrestricted (no common name) Context-sensitive Positive range concatenation Indexed — Linear context-free rewriting systems Tree-adjoining Context-free Deterministic context-free Visibly pushdown Regular — Non-recursive	Recursively enumerable Decidable Context-sensitive Positive range concatenation^* Indexed^* — Linear context-free rewriting language Tree-adjoining Context-free Deterministic context-free Visibly pushdown Regular Star-free Finite	Turing machine Decider Linear-bounded PTIME Turing Machine Nested stack Thread automaton restricted Tree stack automaton Embedded pushdown Nondeterministic pushdown Deterministic pushdown Visibly pushdown Finite Counter-free (with aperiodic finite monoid) Acyclic finite

Each category of languages, except those marked by a ^*, is a proper subset of the category directly above it. Any language in each category is generated by a grammar and by an automaton in the category in the same line.

Digital electronics

Components	Combinational logic Integrated circuit (IC) Logic gate Sequential logic

Theory	Digital signal (electronics) Boolean algebra Logic synthesis Logic in computer science Computer architecture Digital signal (signal processing) Digital signal processing Circuit minimization

Design	Logic synthesis Register-transfer level Formal equivalence checking Synchronous logic Asynchronous logic Finite-state machine

Applications	Computer hardware Digital audio Digital photography Digital video Electronic literature Telecommunication

Design issues	Metastability Runt pulse

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