Logic level

In digital circuits, a logic level is one of a finite number of states that a digital signal can have. Logic levels are usually represented by the voltage difference between the signal and ground, although other standards exist. The range of voltage levels that represents each state depends on the logic family being used.

2-level logic

See also: Boolean algebra

In binary logic the two levels are logical high and logical low, which generally correspond to a binary 1 and 0 respectively. Signals with one of these two levels can be used in boolean logic for digital circuit design or analysis.

Active state

The use of either the higher or the lower voltage level to represent either logic state is arbitrary. The two options are active high and active low. Active-high and active-low states can be mixed at will: for example, a read only memory integrated circuit may have a chip-select signal that is active-low, but the data and address bits are conventionally active-high. Occasionally a logic design is simplified by inverting the choice of active level (see De Morgan's theorem).

Binary signal representations
Logic level Active-high signal Active-low signal
Logical high 1 0
Logical low 0 1

The name of an active-low signal is written with a bar above it to distinguish it from an active-high signal. For example, the name Q, read "Q bar" or "Q not", represents an active-low signal. The conventions commonly used are:

The slash convention is also used with signals that have a meaning in both states. For example, it is common to have a read/write line written R/(W), indicating that the signal is high in case of a read and low in case of a write.

Many control signals in electronics are active-low signals [1] (usually reset lines, chip-select lines and so on). Logic families such as TTL can sink more current than they can source, so fanout and noise immunity increase. It also allows for wired-OR logic if the logic gates are open-collector/open-drain with a pull-up resistor. Examples of this are the I²C bus and the Controller Area Network (CAN),and the PCI Local Bus. RS232 signaling, as used on some serial ports, uses active-low signals.

Logic voltage levels

The two logical states are usually represented by two different voltages, but current is used in some logic families. A threshold is designed for each logic family. When below that threshold, the signal is "low," when above "high". Intermediate levels are undefined and the behavior of the connected circuits is highly implementation-specific.

It is usual to allow some tolerance in the voltage levels used; for example, 0 to 2 volts might represent logic 0, and 3 to 5 volts logic 1. A voltage of 2 to 3 volts would be invalid, and occur only in a fault condition or during a logic level transition. However, few logic circuits can detect such a condition and most devices will interpret the signal simply as high or low in an undefined or device-specific manner. Some logic devices incorporate schmitt trigger inputs whose behavior is much better defined in the threshold region, and have increased resilience to small variations in the input voltage. The problem of the circuit designer is to avoid circumstances that produce intermediate levels, so that the circuit behaves predictably.

Examples of binary logic levels
Technology L voltage H voltage Notes
CMOS[2] 0 V to 1/3 VDD 2/3 VDD to VDD VDD = supply voltage
TTL[2] 0 V to 0.8 V 2 V to VCC VCC = 5 V ±10%
ECL VEE to −1.4 V −1.2 V to 0 V VEE is about −5.2 V; VCC=Ground

Nearly all digital circuits use a consistent logic level for all internal signals. That level, however, varies from one system to another. Interconnecting any two logic families often required special techniques such as additional pull-up resistors or purpose-built interface circuits known as level shifters. A level shifter connects one digital circuit that uses one logic level to another digital circuit that uses another logic level. Often two level shifters are used, one at each system: A line driver converts from internal logic levels to standard interface line levels; a line receiver converts from interface levels to internal voltage levels.

For example, TTL levels are different from those of CMOS. Generally a TTL output does not rise high enough to be reliably recognized as a logic 1 by a CMOS input, especially if it is only connected to a high-input-impedance CMOS input that does not source significant current. This problem was solved by the invention of the 74HCT family of devices that uses CMOS technology but TTL input logic levels. These devices only work with a 5V power supply.

3-level logic

Main article: Three-state logic

In three-state logic, an output device can also be high impedance. This is not a logic level, but means that the output is not controlling the state of the connected circuit.

4-level logic

Main article: Four valued logic

9-level logic

Main article: IEEE 1164

See also

References

  1. ↑ Balch, Mark (2003). Complete Digital Design: A Comprehensive Guide To Digital Electronics And Computer System Architecture. McGraw-Hill Professional. p. 430. ISBN 978-0-07-140927-8.
  2. 1 2 "Logic signal voltage levels". All About Circuits. Retrieved 2015-03-29.

External links

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