MOS Technology 6510

MOS Technology 6510
Common manufacturer(s)
Max. CPU clock rate 0.985 MHz to 1.023 MHz
Package(s)
Image of the internals of a Commodore 64 showing the 6510 CPU (40-pin DIP, lower left). The chip on the right is the 6581 SID. The production week/year (WWYY) of each chip is given below its name.

The MOS Technology 6510 is an 8-bit microprocessor designed by MOS Technology, Inc., and is a modified form of the very successful 6502.

The primary change from the 6502 was the addition of an 8-bit general purpose I/O port (only six I/O pins were available in the most common version of the 6510). In addition, the address bus could be made tristate.

The 6510 was only widely used in the Commodore 64 home computer and its variants. In the C64 the extra I/O pins of the processor were used to control the computer's memory map by bank switching, and in the C64 also for controlling three of the four signal lines of the Datassette tape recorder (the electric motor control, key-press sensing and write data lines; the read data line went to another I/O chip). It was possible, by writing the correct bit pattern to the processor at address $01, to completely expose almost the full 64 KB of RAM in the C64, leaving no ROM or I/O hardware exposed except for the processor I/O port itself and its data directional register.[1]

Variants

Pin configuration of the most common variation of the 6510 CPU (a mistake labels the /RDY pin as /HALT in this image)

MOS 8500

In 1985, MOS produced the 8500, an HMOS version of the 6510. Other than the process change, it is virtually identical to the NMOS version of the 6510. The 8500 was originally designed for use in the modernised C64, the C64C. However, in 1985, limited quantities of 8500s were found on older NMOS-based C64s. It finally made its official debut in 1987, appearing in a motherboard using the new 85xx HMOS chipset.

MOS 7501/8501

The 7501/8501 variant of the 6510 was introduced in 1984.[2] It was used in Commodore's C16, C116 and Plus/4 home computers, where its I/O port controlled not only the Datasette but also the CBM Bus interface. The main difference between 7501 and 8501 CPUs is that they were manufactured with different technologies: 7501 was manufactured with HMOS-1 and 8501 with HMOS-2.[3] The NMI signal are not available for MOS 7501 and MOS 8501.[4]

MOS 8502

The 2 MHz-capable 8502 variant was used in the Commodore 128. All these CPUs are opcode compatible (including undocumented opcodes).[5]

MOS 6510T

The Commodore 1551 disk drive used the 6510T, a version of the 6510 with eight I/O lines. The NMI and RDY signals are not available.

See also

References

  1. ↑ http://www.atarimagazines.com/compute/issue32/112_1_COMMODORE_64_ARCHITECTURE.php
  2. ↑ http://plus4world.powweb.com/hardware/MOS_75018501 Hardware – MOS 7501/8501
  3. ↑ http://plus4world.powweb.com/hardware/MOS_75018501 Hardware – MOS 7501/8501
  4. ↑ The NMI and RDY signals are not available.
  5. ↑ http://www.oxyron.de/html/opcodes02.html
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