Zen (microarchitecture)

Zen is the codename for an upcoming computer processor microarchitecture from AMD, expected for release in early 2017.^[1] The first Zen based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016. The first Zen based CPUs codenamed "Summit Ridge" is expected to have availability starting in 2017, with Zen-derived Opteron server processors expected in the second quarter of 2017,^[8] and Zen-based APUs expected to follow in the second half of 2017.

Zen is a clean sheet design that differs from the long-standing Bulldozer architecture. Zen-based processors use a 14 nm FinFET process, are reportedly more energy efficient, and have a significantly higher IPC. SMT has been introduced, allowing each core to run 2 threads. The cache system has also been redesigned, making the L1 cache write-back. Additionally, Zen based processors will utilize the AM4 socket, bringing DDR4 support.^[9]

Design

According to AMD, the main focus of Zen will be on increasing per-core performance.^[10][11][12]

• L1 cache has been changed from write-through to write-back, allowing for lower latency and higher bandwidth
• SMT (simultaneous multithreading) architecture allows for 2 threads per core, a departure from the CMT (clustered multi-thread) design used in the previous Bulldozer microarchitecture. This is a feature previously offered in some IBM, Intel and Oracle processors.^[13]
• Newly introduced "large" micro-operation cache
• Each SMT core can dispatch up to 6 INT micro-ops and 4 FP micro-ops per cycle (it is unclear whether this means up to 10 micro-ops can be dispatched per cycle)^[14]
• Close to 2x faster L1 and L2 bandwidth, total L3 cache bandwidth up 5x
• Clock gating
• Larger retire, load, and store queues
• Improved branch prediction using a hashed perceptron system similar to the Bobcat microarchitecture,^[15] something that has been compared to a neural network by AMD engineer Mike Clark^[16]
• Branch predictor that is decoupled from the fetch stage
• Dedicated stack engine for modifying the stack pointer, similar to Intel Haswell and Broadwell processors^[17]
• Move elimination, a method that reduces physical data movement to reduce power consumption
• RDSEED support, a high-performance hardware random number generator instructions recently introduced by Intel's CPUs.^[18]

The Zen architecture will be built on a 14 nanometer FINFET process subcontracted to GlobalFoundries,^[20] giving greater efficiency than the 32 nm and 28 nm processes of previous AMD FX CPUs and AMD APUs, respectively.^[21] The "Summit Ridge" Zen family of CPUs will use the AM4 socket and feature DDR4 support and a 95 W TDP.^[21] While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15 W and 15 to 35 W for performance-oriented mobile products with up to four Zen cores.^[22]

Each Zen core can decode four instructions per clock cycle and includes a micro-op cache which feeds two schedulers, one each for the integer and floating point segments.^[23][24] Each core has two address generation units, four integer units, and four floating point units. Two of the floating point units are adders, two are multipliers. There are also improvements in the branch predictor. The L1 cache size is 64 KiB for instructions and 32 KiB for data. The L2 cache size 512 KiB per core, and the L3 is 1-2 MB per core. L3 caches offer 5x the bandwidth of previous AMD designs.

History and development

AMD began planning the Zen microarchitecture shortly after re-hiring Jim Keller in August 2012.^[25]

The team in charge of Zen was led by Keller until he left in September 2015 after a 3-year tenure.^[26]

Zen was originally planned for 2017 following the ARM64-based K12 sister core, but on AMD's 2015 Financial Analyst Day it was revealed that K12 was delayed in favor of the Zen design, to allow it to enter the market within the 2016 timeframe,^[6] with the release of first Zen-based processors expected for October 2016.^[27]

In November 2015 a source inside AMD reported that Zen microprocessors had been tested and "met all expectations" with "no significant bottlenecks found".^[2][28]

In December 2015, it was rumored that Samsung may be contracted as a fabricator for AMD's 14 nm FinFET processors, including both Zen and their then upcoming Polaris GPU architecture.^[29] This was clarified by AMD's July 2016 announcement that products had been successfully produced on Samsung's 14 nm FinFET process.^[30] While AMD stated Samsung would be used "if needed", it was argued this would reduce risk for AMD by decreasing dependence on any one foundry.

Advantages over predecessors

Zen's from-scratch design is notably different from its predecessors, with many different types of changes and enhancements being made across the board in hopes of making Zen more competitive with Intel's architectures, and the software most often built with Intel's processor features in mind.

Manufacturing process

Processors built using Zen will utilize 14 nm FinFET silicon.^[31] These processors are being produced at GlobalFoundries,^[32] though reports state some Zen processors may also be produced at TSMC.^[33] Prior to Zen, AMD's smallest process size was 28 nm, as utilized by their Steamroller and Excavator microarchitectures.^[34][35] The immediate competition, Intel's Skylake and Kaby Lake microarchitecture, are also fabricated on 14 nm FinFET;^[36] though Intel is planning to begin the release of 10 nm parts in 2017.^[37]

For identical designs, these die shrinks would use less current (and power) at the same frequency (or voltage). As CPUs are usually power limited (typically up to ~125W, or ~45W for mobile), smaller transistors allow for either lower power at the same frequency, or higher frequency at the same power.^[38]

Performance

One of Zen's major goals is to focus on performance per-core, and it is targeting a 40% improvement in instructions per clock over its predecessor.^[39] Excavator, in comparison, offered 4-15% improvement over previous architectures.^[40][41] The inclusion of SMT also allows each core to process up to two threads, increasing processing throughput by better utilizing available resources.

AMD has demonstrated an 8-core/16-thread Zen processor outperforming an equally-clocked Intel Broadwell-E processor in a Blender rendering benchmark.^[1][8]

Memory

APUs utilizing the Zen architecture will also support High Bandwidth Memory (HBM).^[42] Previous APUs from AMD had to rely on traditional shared DDR3 RAM for video memory.

Zen supports DDR4 memory (up to 8 channels).^[43] Previous CPUs and APUs from AMD only supported up to DDR3.

Power consumption and heat output

Processors built at the 14 nm node on FinFET silicon should show reduced power consumption and therefore heat over their 28 nm and 32 nm non-FinFET predecessors (for equivalent designs), or be more computationally powerful at equivalent heat output/power consumption.

Zen is also expected to utilize clock gating to further reduce power consumption,^[24] reducing the frequency of underutilized portions of the core to save power.

Enhanced security and virtualization support

Zen added the support for AMD's Secure Memory Encryption (SME) and AMD's Secure Encrypted Virtualization (SEV). Secure Memory Encryption is real time memory encryption done per page table entry. This is done utilizing the onboard "Security" Processor (ARM Cortex-A5) at boot time to encrypt each page, allowing any DDR-4 memory (including nonvolatile varieties) to be encrypted. AMD SME also makes the contents of the memory more resistant to memory snooping and cold boot attacks.^[44][45]

^[46]

Products

Zen is expected to be utilized in future desktop FX CPUs, future Opteron server processors, and future APUs.^[42][47][48]

The first desktop processors without graphics processing unit (codename: "Summit Ridge") was expected start selling at the end of 2016, according to an AMD roadmap; with the first mobile and desktop processors of the AMD Accelerated Processing Unit type (codename: "Raven Ridge") following in 2017.^[49] AMD officially delayed Zen until 2017 in August 2016, while demonstrating an 8-core/16-thread at 3 GHz.^[8] Final clock speeds and TDPs have not been announced. AMD also demonstrated a dual socket server platform running two Zen processors with 32-core/64-thread each.^[1][8]

See also

• AMD K9
• AMD K10
• Steamroller (microarchitecture)

References